HS PF
DE

Prof. Dr. rer. nat.

Peer Johannsen

Contact

Room

T2.2.18

Colloquium

Forschungssemester

Phone

(07231) 28-6166

Mail

peer.johannsen(at)hs-pforzheim(dot)de
  • Computer Science, Algorithms, Logic
  • Software Development, Programming Techniques
  • Puzzle Based Learning in Computer Science
  • Robotics, Robot Programming
  • Formal Hardware Verification

Certified Roberta-Teacher (Fraunhofer IAIS Initiative "Learning with Robots")

2015

Hochschullehrpreis der Hochschule Pforzheim


2014

Lehrpreis der Fakultät für Technik


1998 - 2001

Forschungsstipendium der Siemens AG, München


1997

Kieler Informatik Preis


Computer Science

Journal article

JOHANNSEN, P. (2013). 8 Bit sind auch heute noch ein Byte.


Dissertation

JOHANNSEN, P. (2003). Speeding Up Hardware Verification bu Automated Data Path Scaling. Christian-Albrechts-Universität zu Kiel. Kiel, Germany.


Chapter in Book

JOHANNSEN, P., BRINKMANN, R., WINKELMANN, K. (2004). Application of Property Checking and Underlying Techniques. In R. Drechsler (Ed.), Advanced Formal Verification (pp. 125-166). Kluwer Academic Publishers.

JOHANNSEN, P., DRECHSLER, R. (2002). Utilizing High-Level Information for Formal Hardware Verification. In J. Soldek and J. Pejas (Ed.), Advanced Computer Systems (pp. 419-431). Kluwer Academic Publishers.


Article in Proceedings

JOHANNSEN, P. (2013). Robots, Card Tricks and Creative Problem Solving. AETMS 2013.

JOHANNSEN, P. (2013). Robotics meets Puzzle Based Learning. NAO Tech Day 2013.

JOHANNSEN, P. (2013). Robots, Card Tricks and Creative Problem Solving.

JOHANNSEN, P. (2013). Robotics meets Puzzle Based Learning.

JOHANNSEN, P. (2011). True, unless disproven, or false, unless verified? Avoiding False Negatives in Functional Verification of Digital Circuits. 45. Workshop, Multi Project Chip Group.

JOHANNSEN, P., DRECHSLER, R. (2001). Speeding Up Verification of RTL Designs by Computing One-To-One Abstractions with Reduced Signal Widths. VLSI 2001 Post Conference Book, Kluwer Academic Publishers.

JOHANNSEN, P., DRECHSLER, R. (2001). Formal Verification on the RT-Level, Computing One-To One Design Abstractions by Signal-Width Reduction. Proc. VLSI-SOC 2001 (11th International Conference on Very Large Scale Integration of Systems On-Chip, Montpellier, Frankreich).

JOHANNSEN, P., DRECHSLER, R. (2001). Utilizing High-Level Information for Formal Hardware Verification. Proc. ACS 2001 (Advanced Computer Systems, 8th International Conference, Mielno, Polen).

JOHANNSEN, P. (2001). BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction. Proc. CAV 2001 (Computer Aided Verification, 13th International Conference, Paris, Frankreich).

JOHANNSEN, P. (2001). Reducing Bitvector Satisfiability Problems to Scale Down Design Sizes for RTL Property Checking. IEEE Proc. HLDVT 2001 (6th IEEE International High-Level Design Validation and Test Workshop, Monterey, Kalifornien, USA).


Online Publication

JOHANNSEN, P. (2012). Mechatronics meets Computer Science.


Scientific Paper/Report

JOHANNSEN, P., STABER, S. (2009). Verifikation parametrisierter Schaltungsbeschreibungen. Germany.


Academic Papers of Pforzheim University

JOHANNSEN, P. (2016). Retro Programming - Video-Spiele, Vektor-Graphik, und Wissenschaft einmal anders. Germany.

JOHANNSEN, P. (2013). 30 Jahre alter Atari 130 XE Computer veranschaulicht Informatik und Digitaltechnik. Germany.

JOHANNSEN, P. (2012). Heute erleben, was morgen unseren Alltag prägt. Germany.